High Frequency High Efficiency Voltage Regulators For Future Microprocessors
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High Frequency High-efficiency Voltage Regulators for Future Microprocessors by Anonim Pdf
Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us. The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future.
Voltage Regulators for Next Generation Microprocessors by Toni López,Reinhold Elferich,Eduard Alarcón Pdf
This book deals with energy delivery challenges of the power processing unit of modern computer microprocessors. It describes in detail the consequences of current trends in miniaturization and clock frequency increase, upon the power delivery unit, referred to as voltage regulator. This is an invaluable reference for anybody needing to understand the key performance limitations and opportunities for improvement, from both a circuit and systems perspective, of state-of-the-art power solutions for next generation CPUs.
Low Power Circuits for Emerging Applications in Communications, Computing, and Sensing by Fei Yuan Pdf
The book addresses the need to investigate new approaches to lower energy requirement in multiple application areas and serves as a guide into emerging circuit technologies. It explores revolutionary device concepts, sensors, and associated circuits and architectures that will greatly extend the practical engineering limits of energy-efficient computation. The book responds to the need to develop disruptive new system architecutres, circuit microarchitectures, and attendant device and interconnect technology aimed at achieving the highest level of computational energy efficiency for general purpose computing systems. Features Discusses unique technologies and material only available in specialized journal and conferences Covers emerging applications areas, such as ultra low power communications, emerging bio-electronics, and operation in extreme environments Explores broad circuit operation, ex. analog, RF, memory, and digital circuits Contains practical applications in the engineering field, as well as graduate studies Written by international experts from both academia and industry
Advances in Renewable Energies and Power Quality by Manuel Pérez-Donsión,Gianpaolo Vitale Pdf
This volume brings together contributions dealing with renewable energies and power quality, presented over five years of the International Conference on Renewable Energy and Power Quality (ICREPQ). It contains a selection of the best papers and original contributions presenting state-of-the-art research in the field of renewable energy sources. Including some of the leading authorities in their areas of expertise, the contributors to the volume are drawn from across the globe, with about 300 authors from 60 different countries.
Analog Circuit Design by Michiel Steyaert,Arthur H.M. van Roermund,Herman Casier Pdf
Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design.
Architecture and Circuit Cross-cutting Approaches for Power-efficient Multi-core Processors by Hamid Reza Ghasemi Pdf
With technology scaling, which allows manufacturers to integrate more cores per chip, the per-formance of multi-core processors has been increased for the past decade. However, such a trend can-not be sustained because the power reduction per core has slowed down, while the maximum power consumption allowed per chip has not increased. This limits the maximum number of cores per chip. Therefore, improving the power efficiency of the existing and future multi-core processors becomes crucial for higher performance. Traditionally, dynamic voltage and frequency scaling (DVFS) has been the most powerful technique to enable power-efficient multi-core processing. However, with aggressive technology scal-ing, the efficiency of DVFS has been continuously decreased due to the shrinking voltage scaling win-dow. Prior efforts to improve the efficiency of DVFS often have not been (cost) effective. Besides, most of these solutions may be sub-optimal since they investigate only one abstraction layer: circuit or micro-architecture. Although solutions focusing on one abstraction layer reduce the complexity of the design process, they may increase inefficiencies in design by not exploiting the shared goals, limita-tions, and requirements across multiple design layers. This dissertation discusses existing challenges to improve the power efficiency of multi-core processors, and proposes circuit and architecture cross-cutting techniques to further improve power efficiency of future multi-core processors. This dissertation identifies various challenges involved in the efficiency of DVFS and proposes solutions to overcome these challenges. In addition, it proposes power efficiency techniques that are independent from and/or orthogonal to DVFS. In this dissertation, I make four main contributions: First, I demonstrate a cost-effective power delivery technique to support per-core voltage do-mains for power-constrained multi-core processors. I exploit a very low-cost voltage regulator (VR) that uses the existing on-chip per-core power-gating (PCPG) devices available in most commercial processors and optimize a DVFS algorithm to efficiently work with this special VR. This technique considerably reduces the cost of VRs while it provides highly power-efficient per-core DVFS. Second, I propose a last-level cache (LLC) architecture comprised of heterogeneous cell sizes to deliver both high-performance and low minimum operating voltage (VDDMIN). For low-power oper-ation, the proposed LLC exclusively uses large cells that exhibit low failure rates at low voltages, ena-bling it to operate at low VDDMIN. For high-performance operation, it operates at a high enough volt-age at which the failure rate of even small cells of the LLC is sufficiently low, providing the needed large LLC capacity. Third, I propose a new technique to dynamically scale the number of cores and the amount of resources of processors for increasing power efficiency when DVFS technique becomes not a viable option for future processors. This technique is a DVFS alternative that can trade performance with power consumption through micro-architectural resource scaling mechanism (instead of volt-age/frequency) to maximize performance under a power constraint. It also proposes a runtime policy that can effectively manage and leverage the proposed architectural mechanism to maximize perfor-mance under a power constraint. Finally, I present a technique to dynamically adjust voltage regulators (VRs) to improve power efficiency. The VRs are the most critical component of processor power delivery sub-system and dis-sipates high power that is directly proportional to the power consumed by the processor. Traditionally, when a processor is in active state, all phases of VR will be active regardless of power consumption of processor. This leads to poor VR efficiency. This technique scales up and down the number of VR's active phases, by predicting the load current of processors, to increase the VR efficiency and reduce the VR's dissipated power. With these mechanisms and analysis, this dissertation demonstrates multiple architecture/circuit techniques to improve power efficiency of multi-core processors when traditional DVFS technique is not efficient or not a viable solution.
On-Chip Photonic Interconnects by Christopher J. Nitta,Matthew Farrens,Venkatesh Akella Pdf
As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks.
9th International Conference on Robotic, Vision, Signal Processing and Power Applications by Haidi Ibrahim,Shahid Iqbal,Soo Siang Teoh,Mohd Tafir Mustaffa Pdf
The proceeding is a collection of research papers presented, at the 9th International Conference on Robotics, Vision, Signal Processing & Power Applications (ROVISP 2016), by researchers, scientists, engineers, academicians as well as industrial professionals from all around the globe to present their research results and development activities for oral or poster presentations. The topics of interest are as follows but are not limited to: • Robotics, Control, Mechatronics and Automation • Vision, Image, and Signal Processing • Artificial Intelligence and Computer Applications • Electronic Design and Applications • Telecommunication Systems and Applications • Power System and Industrial Applications • Engineering Education
Three-Dimensional Integrated Circuit Design by Yuan Xie,Jingsheng Jason Cong,Sachin Sapatnekar Pdf
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
Integrated Power Devices and TCAD Simulation by Yue Fu,Zhanming Li,Wai Tung Ng,Johnny K.O. Sin Pdf
From power electronics to power integrated circuits (PICs), smart power technologies, devices, and beyond, Integrated Power Devices and TCAD Simulation provides a complete picture of the power management and semiconductor industry. An essential reference for power device engineering students and professionals, the book not only describes the physics inside integrated power semiconductor devices such lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOSFETs), lateral insulated-gate bipolar transistors (LIGBTs), and super junction LDMOSFETs but also delivers a simple introduction to power management systems. Instead of abstract theoretical treatments and daunting equations, the text uses technology computer-aided design (TCAD) simulation examples to explain the design of integrated power semiconductor devices. It also explores next generation power devices such as gallium nitride power high electron mobility transistors (GaN power HEMTs). Including a virtual process flow for smart PIC technology as well as a hard-to-find technology development organization chart, Integrated Power Devices and TCAD Simulation gives students and junior engineers a head start in the field of power semiconductor devices while helping to fill the gap between power device engineering and power management systems.
