Low Voltage Cmos Log Companding Analog Design

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Low-Voltage CMOS Log Companding Analog Design

Francisco Serra-Graells,Adoración Rueda,José L. Huertas
Low Voltage CMOS Log Companding Analog Design Book PDF

Author : Francisco Serra-Graells,Adoración Rueda,José L. Huertas
Publisher : Springer Science & Business Media
Page : 192 pages
File Size : 48,6 Mb
Release : 2006-04-18
Category : Technology & Engineering
ISBN : 9780306487217

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Low-Voltage CMOS Log Companding Analog Design by Francisco Serra-Graells,Adoración Rueda,José L. Huertas Pdf

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems

Vincent S.L. Cheung,Howard Cam H. Luong
Design of Low Voltage CMOS Switched Opamp Switched Capacitor Systems Book PDF

Author : Vincent S.L. Cheung,Howard Cam H. Luong
Publisher : Springer Science & Business Media
Page : 207 pages
File Size : 41,7 Mb
Release : 2013-03-14
Category : Technology & Engineering
ISBN : 9781475737011

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Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems by Vincent S.L. Cheung,Howard Cam H. Luong Pdf

This volume emphasizes the design and development of advanced switched-opamp architectures and techniques for low-voltage low-power switched-capacitor systems. It presents a novel multi-phase switched-opamp technique together with new system architectures that are critical in improving significantly the performance of switched-capacitor systems at low supply voltages.

Low-Power Deep Sub-Micron CMOS Logic

P. van der Meer,A. van Staveren,Arthur H.M. van Roermund
Low Power Deep Sub Micron CMOS Logic Book PDF

Author : P. van der Meer,A. van Staveren,Arthur H.M. van Roermund
Publisher : Springer Science & Business Media
Page : 165 pages
File Size : 44,7 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781402028496

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Low-Power Deep Sub-Micron CMOS Logic by P. van der Meer,A. van Staveren,Arthur H.M. van Roermund Pdf

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

Rene van Leuken,Gilles Sicard
Integrated Circuit and System Design Power and Timing Modeling Optimization and Simulation Book PDF

Author : Rene van Leuken,Gilles Sicard
Publisher : Springer Science & Business Media
Page : 270 pages
File Size : 53,7 Mb
Release : 2011-02-04
Category : Computers
ISBN : 9783642177514

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation by Rene van Leuken,Gilles Sicard Pdf

This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters

Rudy J. van de Plassche
CMOS Integrated Analog to Digital and Digital to Analog Converters Book PDF

Author : Rudy J. van de Plassche
Publisher : Springer Science & Business Media
Page : 628 pages
File Size : 50,7 Mb
Release : 2013-04-17
Category : Technology & Engineering
ISBN : 9781475737684

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CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters by Rudy J. van de Plassche Pdf

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters.

Systematic Design of Analog IP Blocks

Jan Vandenbussche,Georges Gielen,Michiel Steyaert
Systematic Design of Analog IP Blocks Book PDF

Author : Jan Vandenbussche,Georges Gielen,Michiel Steyaert
Publisher : Springer Science & Business Media
Page : 205 pages
File Size : 46,9 Mb
Release : 2013-03-14
Category : Technology & Engineering
ISBN : 9781475737073

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Systematic Design of Analog IP Blocks by Jan Vandenbussche,Georges Gielen,Michiel Steyaert Pdf

This book introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified. To validate the presented methodologies, the authors have selected and designed accordingly three different industrial-strength applications.

Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation

Federico Bruccoleri,Eric Klumperink,Bram Nauta
Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation Book PDF

Author : Federico Bruccoleri,Eric Klumperink,Bram Nauta
Publisher : Springer Science & Business Media
Page : 182 pages
File Size : 48,5 Mb
Release : 2006-03-30
Category : Technology & Engineering
ISBN : 9781402031885

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Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation by Federico Bruccoleri,Eric Klumperink,Bram Nauta Pdf

Low Noise Amplifiers (LNAs) are commonly used to amplify signals that are too weak for direct processing for example in radio or cable receivers. Traditionally, low noise amplifiers are implemented via tuned amplifiers, exploiting inductors and capacitors in resonating LC-circuits. This can render very low noise but only in a relatively narrow frequency band close to resonance. There is a clear trend to use more bandwidth for communication, both via cables (e.g. cable TV, internet) and wireless links (e.g. satellite links and Ultra Wideband Band). Hence wideband low-noise amplifier techniques are very much needed. Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation explores techniques to realize wideband amplifiers, capable of impedance matching and still achieving a low noise figure well below 3dB. This can be achieved with a new noise cancelling technique as described in this book. By using this technique, the thermal noise of the input transistor of the LNA can be cancelled while the wanted signal is amplified! The book gives a detailed analysis of this technique and presents several new amplifier circuits. This book is directly relevant for IC designers and researchers working on integrated transceivers. Although the focus is on CMOS circuits, the techniques can just as well be applied to other IC technologies, e.g. bipolar and GaAs, and even in discrete component technologies.

Mixed-Signal Layout Generation Concepts

Chieh Lin,Arthur H.M. van Roermund,Domine Leenaerts
Mixed Signal Layout Generation Concepts Book PDF

Author : Chieh Lin,Arthur H.M. van Roermund,Domine Leenaerts
Publisher : Springer Science & Business Media
Page : 210 pages
File Size : 41,9 Mb
Release : 2005-12-17
Category : Computers
ISBN : 9780306487255

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Mixed-Signal Layout Generation Concepts by Chieh Lin,Arthur H.M. van Roermund,Domine Leenaerts Pdf

This title covers important physical-design issues that exist in contemporary analogue and mixed-signal design flows. The authors bring together many principles and techniques required to successfully develop and implement layout generation tools to accommodate many mixed-signal layout generation needs.

Operational Amplifier Speed and Accuracy Improvement

Vadim V. Ivanov,Igor M. Filanovsky
Operational Amplifier Speed and Accuracy Improvement Book PDF

Author : Vadim V. Ivanov,Igor M. Filanovsky
Publisher : Springer Science & Business Media
Page : 194 pages
File Size : 42,8 Mb
Release : 2006-04-18
Category : Technology & Engineering
ISBN : 9781402025174

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Operational Amplifier Speed and Accuracy Improvement by Vadim V. Ivanov,Igor M. Filanovsky Pdf

Operational Amplifier Speed and Accuracy Improvement proposes a new methodology for the design of analog integrated circuits. The usefulness of this methodology is demonstrated through the design of an operational amplifier. This methodology consists of the following iterative steps: description of the circuit functionality at a high level of abstraction using signal flow graphs; equivalent transformations and modifications of the graph to the form where all important parameters are controlled by dedicated feedback loops; and implementation of the structure using a library of elementary cells. Operational Amplifier Speed and Accuracy Improvement shows how to choose structures and design circuits which improve an operational amplifier's important parameters such as speed to power ratio, open loop gain, common-mode voltage rejection ratio, and power supply rejection ratio. The same approach is used to design clamps and limiting circuits which improve the performance of the amplifier outside of its linear operating region, such as slew rate enhancement, output short circuit current limitation, and input overload recovery.

Systematic Modeling and Analysis of Telecom Frontends and their Building Blocks

Piet Vanassche,Georges Gielen,Willy M Sansen
Systematic Modeling and Analysis of Telecom Frontends and their Building Blocks Book PDF

Author : Piet Vanassche,Georges Gielen,Willy M Sansen
Publisher : Springer Science & Business Media
Page : 243 pages
File Size : 42,8 Mb
Release : 2005-10-24
Category : Technology & Engineering
ISBN : 9781402031748

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Systematic Modeling and Analysis of Telecom Frontends and their Building Blocks by Piet Vanassche,Georges Gielen,Willy M Sansen Pdf

To meet the demands of today's highly competitive market, analog electronics designers must develop their IC designs in a minimum of time. The difference between first- and second-time right seriously affects a company's share of the market. Analog designers are therefore in need for structured design methods together with the theory and tools to support them, especially when pushing the performance limits in high-performance designs. Systematic Modeling and Analysis of Telecom Frontends and Their Building Blocks aims to help designers in speeding up telecommunication frontend design by offering an in-depth understanding of the frontend's behavior together with methods and algorithms that support designers in bringing this understanding to practice. The book treats topics such as time-varying phase-locked loop stability, noise in mixing circuits, oscillator injection locking, oscillator phase noise behavior, harmonic oscillator dynamics and many more. In doing so, it always starts from a theoretical foundation that is both rigorous and general. Phase-locked loop and mixer analysis, for example, are grounded upon a general framework for time-varying small-signal analysis. Likewise, analysis of harmonic oscillator transient behavior and oscillator phase noise analysis are treated as particular applications of a general framework for oscillator perturbation analysis. In order to make the book as easy to read as possible, all theory is always accompanied by numerous examples and easy-to-catch intuitive explanations. As such, the book is suited for both computer-aided design engineers looking for general theories and methods, either as background material or for practical implementation in tools, as well as for practicing circuit designers looking for help and insight in dealing with a particular application or a particular high-performance design problem.

Design of Wireless Autonomous Datalogger IC's

Wim Claes,Willy M Sansen,Robert Puers
Design of Wireless Autonomous Datalogger IC s Book PDF

Author : Wim Claes,Willy M Sansen,Robert Puers
Publisher : Springer Science & Business Media
Page : 211 pages
File Size : 46,7 Mb
Release : 2006-03-30
Category : Technology & Engineering
ISBN : 9781402032097

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Design of Wireless Autonomous Datalogger IC's by Wim Claes,Willy M Sansen,Robert Puers Pdf

Design of Wireless Autonomous Dataloggers IC's reveals the state of the art in the design of complex dataloggers, with a special focus on low power consumption. The emphasis is on autonomous dataloggers for stand-alone applications with remote reprogrammability. The book starts with a comprehensive introduction on the most important design aspects and trade-offs for miniaturized low-power telemetric dataloggers. After the general introduction follows an in-depth case study of an autonomous CMOS datalogger IC for the registration of in vivo loads on oral implants. After tackling the design of the datalogger on the system level, the design of the different building blocks is elaborated in detail, with emphasis on low power. A clear overview of the operation, the implementation, and the most important design considerations of the building blocks to achieve optimal system performance is given. Design of Wireless Autonomous Dataloggers IC's discusses the design of correlated double sampling amplifiers and sample-and-holds, binary-weighted current steering DACs, successive approximation ADCs and relaxation clock oscillators and can also be used as a manual for the design of these building blocks. Design of Wireless Autonomous Dataloggers IC's covers the complete design flow of low-power miniaturized autonomous dataloggers with a bi-directional wireless link and on-board data processing, while providing detailed insight into the most critical design issues of the different building blocks. It will allow you to design complex dataloggers faster. It is essential reading for analog design engineers and researchers in the field of miniaturized dataloggers and is also suitable as a text for an advanced course on the subject.

Dynamic Characterisation of Analogue-to-Digital Converters

Dominique Dallet,José Machado da Silva
Dynamic Characterisation of Analogue to Digital Converters Book PDF

Author : Dominique Dallet,José Machado da Silva
Publisher : Springer Science & Business Media
Page : 291 pages
File Size : 48,6 Mb
Release : 2006-03-08
Category : Technology & Engineering
ISBN : 9780387259031

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Dynamic Characterisation of Analogue-to-Digital Converters by Dominique Dallet,José Machado da Silva Pdf

The Analogue-to-digital converter (ADC) is the most pervasive block in electronic systems. With the advent of powerful digital signal processing and digital communication techniques, ADCs are fast becoming critical components for system’s performance and flexibility. Knowing accurately all the parameters that characterise their dynamic behaviour is crucial, on one hand to select the most adequate ADC architecture and characteristics for each end application, and on the other hand, to understand how they affect performance bottlenecks in the signal processing chain. Dynamic Characterisation of Analogue-to-Digital Converters presents a state of the art overview of the methods and procedures employed for characterising ADCs’ dynamic performance behaviour using sinusoidal stimuli. The three classical methods – histogram, sine wave fitting, and spectral analysis – are thoroughly described, and new approaches are proposed to circumvent some of their limitations. This is a must-have compendium, which can be used by both academics and test professionals to understand the fundamental mathematics underlining the algorithms of ADC testing, and as an handbook to help the engineer in the most important and critical details for their implementation.

Static and Dynamic Performance Limitations for High Speed D/A Converters

Anne van den Bosch,Michiel Steyaert,Willy M.C. Sansen
Static and Dynamic Performance Limitations for High Speed D A Converters Book PDF

Author : Anne van den Bosch,Michiel Steyaert,Willy M.C. Sansen
Publisher : Springer Science & Business Media
Page : 229 pages
File Size : 40,7 Mb
Release : 2013-06-29
Category : Technology & Engineering
ISBN : 9781475765793

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Static and Dynamic Performance Limitations for High Speed D/A Converters by Anne van den Bosch,Michiel Steyaert,Willy M.C. Sansen Pdf

Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters. Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.

Matching Properties of Deep Sub-Micron MOS Transistors

Jeroen A. Croon,Willy M Sansen,Herman E. Maes
Matching Properties of Deep Sub Micron MOS Transistors Book PDF

Author : Jeroen A. Croon,Willy M Sansen,Herman E. Maes
Publisher : Springer Science & Business Media
Page : 206 pages
File Size : 49,6 Mb
Release : 2006-06-20
Category : Technology & Engineering
ISBN : 9780387243139

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Matching Properties of Deep Sub-Micron MOS Transistors by Jeroen A. Croon,Willy M Sansen,Herman E. Maes Pdf

Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction: A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter. The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters. The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance. The impact of process parameters on the matching properties is discussed. The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor. Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.

A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices

Jordi Colomer-Farrarons,Pere MIRIBEL
A CMOS Self Powered Front End Architecture for Subcutaneous Event Detector Devices Book PDF

Author : Jordi Colomer-Farrarons,Pere MIRIBEL
Publisher : Springer Science & Business Media
Page : 163 pages
File Size : 50,8 Mb
Release : 2011-02-17
Category : Technology & Engineering
ISBN : 9789400706866

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A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices by Jordi Colomer-Farrarons,Pere MIRIBEL Pdf

A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc... that are detected through a three-electrodes amperometric BioSensor approach. The device is envisaged as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the skin. The sensor is controlled with a Potentiostat circuit and then, a post-processing unit detects the desired levels and activates the transmission via a backscattering method by the inductive link. All the instrumentation, except the power module, is implemented in the so called BioChip. Following the idea of the powering link to harvest energy of the magnetic induced link at the implanted device, a Multi-Harvesting Power Chip (MHPC) has been also designed.