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Author : J. W Dally
Publisher : Unknown
Page : 270 pages
File Size : 55,6 Mb
Release : 1987-09-01
Category : Electronic
ISBN : 146131996X
Author : J. W. Dally
Publisher : Springer Science & Business Media
Page : 256 pages
File Size : 44,5 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461319955
Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and commu nication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures. Concurrent Smalltalk (CST), a derivative of Smalltalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the nodes of a concurrent computer. These distributed objects have many constituent objects and thus can process many messages simultaneously. They are the foundation upon which concurrent data structures are built. The balanced cube is a concurrent data structure for ordered sets. The set is distributed by a balanced recursive partition that maps to the subcubes of a binary 7lrcube using a Gray code. A search algorithm, VW search, based on the distance properties of the Gray code, searches a balanced cube in O(log N) time. Because it does not have the root bottleneck that limits all tree-based data structures to 0(1) concurrency, the balanced cube achieves 0C.:N) con currency. Considering graphs as concurrent data structures, graph algorithms are pre sented for the shortest path problem, the max-flow problem, and graph parti tioning. These algorithms introduce new synchronization techniques to achieve better performance than existing algorithms.
Author : R.Michael Hord
Publisher : CRC Press
Page : 421 pages
File Size : 44,9 Mb
Release : 2018-02-01
Category : Computers
ISBN : 9781351083782
Parallel Supercomputing in MIMD Architectures is devoted to supercomputing on a wide variety of Multiple-Instruction-Multiple-Data (MIMD)-class parallel machines. This book describes architectural concepts, commercial and research hardware implementations, major programming concepts, algorithmic methods, representative applications, and benefits and drawbacks. Commercial machines described include Connection Machine 5, NCUBE, Butterfly, Meiko, Intel iPSC, iPSC/2 and iWarp, DSP3, Multimax, Sequent, and Teradata. Research machines covered include the J-Machine, PAX, Concert, and ASP. Operating systems, languages, translating sequential programs to parallel, and semiautomatic parallelizing are aspects of MIMD software addressed in Parallel Supercomputing in MIMD Architectures. MIMD issues such as scalability, partitioning, processor utilization, and heterogenous networks are discussed as well.This book is packed with important information and richly illustrated with diagrams and tables, Parallel Supercomputing in MIMD Architectures is an essential reference for computer professionals, program managers, applications system designers, scientists, engineers, and students in the computer sciences.
Author : Emile H.L. Aarts,Jan van Leeuwen,Martin Rem
Publisher : Springer
Page : 942 pages
File Size : 43,8 Mb
Release : 2013-11-11
Category : Computers
ISBN : 9783662252093
The innovative progress in the development oflarge-and small-scale parallel computing systems and their increasing availability have caused a sharp rise in interest in the scientific principles that underlie parallel computation and parallel programming. The biannual "Parallel Architectures and Languages Europe" (PARLE) conferences aim at presenting current research material on all aspects of the theory, design, and application of parallel computing systems and parallel processing. At the same time, the goal of the PARLE conferences is to provide a forum for researchers and practitioners to ex change ideas on recent developments and trends in the field of parallel com puting and parallel programming. The first ~wo conferences, PARLE '87 and PARLE '89, have succeeded in meeting this goal and made PARLE a conference that is recognized worldwide in the field of parallel computation. PARLE '91 again offers a wealth of high-quality research material for the benefit of the scientific community. Compared to its predecessors, the scope of PARLE '91 has been broadened so as to cover the area of parallel algo rithms and complexity, in addition to the central themes of parallel archi tectures and languages. The proceedings of the PARLE '91 conference contain the text of all con tributed papers that were selected for the programme and of the invited papers by leading experts in the field.
Author : Stewart G. Smith,Peter B. Denyer
Publisher : Springer Science & Business Media
Page : 246 pages
File Size : 42,8 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461320159
This book is concerned with advances in serial-data computa tional architectures, and the CAD tools for their implementation in silicon. The bit-serial tradition at Edinburgh University (EU) stretches back some 6 years to the conception of the FIRST silicon compiler. FIRST owes much of its inspiration to Dick Lyon, then at Xerox P ARC, who proposed a 'structured-design' methodology for construction of signal processing systems from bit-serial building blocks. Based on an nMOS cell-library, FIRST automates much of Lyon's physical design process. More recently, we began to feel that FIRST should be able to exploit more modern technologies. Before this could be achieved, we were faced with a massive manual re-design task, i. e. the porting of FIRST cell-library to a new technology. As it was to avoid such tasks that FIRST was conceived in the first place, we decided to move the level of user-specification much nearer to the silicon level (while still hiding details of transistor circuit design, place and route etc. , from the user), and by so doing, enable the specification of more functionally powerful libraries in technology-free form. The results of this work are in evidence as advances in serial-data design techniques, and the SECOND silicon compiler, introduced later in this book. These achievements could not have been accomplished without help from various sources. We take this opportunity to thank Profs.
Author : Dorothy E. Setliff,Rob A. Rutenbar
Publisher : Springer Science & Business Media
Page : 237 pages
File Size : 52,7 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461315513
This book, and the research it describes, resulted from a simple observation we made sometime in 1986. Put simply, we noticed that many VLSI design tools looked "alike". That is, at least at the overall software architecture level, the algorithms and data structures required to solve problem X looked much like those required to solve problem X'. Unfortunately, this resemblance is often of little help in actually writing the software for problem X' given the software for problem X. In the VLSI CAD world, technology changes rapidly enough that design software must continually strive to keep up. And of course, VLSI design software, and engineering design software in general, is often exquisitely sensitive to some aspects of the domain (technology) in which it operates. Modest changes in functionality have an unfortunate tendency to require substantial (and time-consuming) internal software modifications. Now, observing that large engineering software systems are technology dependent is not particularly clever. However, we believe that our approach to xiv Preface dealing with this problem took an interesting new direction. We chose to investigate the extent to which automatic programming ideas cold be used to synthesize such software systems from high-level specifications. This book is one of the results of that effort.
Author : Ronald V. Book
Publisher : Springer Science & Business Media
Page : 900 pages
File Size : 52,6 Mb
Release : 1991-03-27
Category : Computers
ISBN : 3540539042
This volume contains the proceedings of the Fourth International Conference on Rewriting Techniques and Applications (RTA-91), held in Como, Italy, April 10-12, 1991. The volume includes 40 papers on a wide variety of topics including: term rewriting systems, equational unification, algebraic rewriting, termination proofs, generalization problems, undecidable properties, parametrized specifications, normalizing systems, program transformation, query optimization, tree languages, graph languages, theorem proving systems, completion, graph rewriting systems, and open problems.
Author : Allen M. Dewey,Stephen W. Director
Publisher : Springer Science & Business Media
Page : 230 pages
File Size : 41,8 Mb
Release : 1990-05-31
Category : Computers
ISBN : 0792391020
This book describes a new type of computer aided VLSI design tool, called a VLSI System Planning, that is meant to aid designers dur ing the early, or conceptual, state of design. During this stage of design, the objective is to define a general design plan, or approach, that is likely to result in an efficient implementation satisfying the initial specifications, or to determine that the initial specifications are not realizable. A design plan is a collection of high level design decisions. As an example, the conceptual design of digital filters involves choosing the type of algorithm to implement (e. g. , finite impulse response or infinite impulse response), the type of polyno mial approximation (e. g. , Equiripple or Chebyshev), the fabrication technology (e. g. , CMOS or BiCMOS), and so on. Once a particu lar design plan is chosen, the detailed design phase can begin. It is during this phase that various synthesis, simulation, layout, and test activities occur to refine the conceptual design, gradually filling more detail until the design is finally realized. The principal advantage of VLSI System Planning is that the increasingly expensive resources of the detailed design process are more efficiently managed. Costly redesigns are minimized because the detailed design process is guided by a more credible, consistent, and correct design plan.
Author : Debashis Bhattacharya,John P. Hayes
Publisher : Springer Science & Business Media
Page : 168 pages
File Size : 47,8 Mb
Release : 2012-12-06
Category : Computers
ISBN : 9781461315278
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Author : Mohammed Ismail,José E. Franca
Publisher : Springer Science & Business Media
Page : 191 pages
File Size : 55,5 Mb
Release : 2012-12-06
Category : Computers
ISBN : 9781461315353
Very large scale integration (VLSI) technologies are now maturing with a current emphasis toward submicron structures and sophisticated applications combining digital as well as analog circuits on a single chip. Abundant examples are found on today's advanced systems for telecom munications, robotics, automotive electronics, image processing, intelli gent sensors, etc .. Exciting new applications are being unveiled in the field of neural computing where the massive use of analog/digital VLSI technologies will have a significant impact. To match such a fast technological trend towards single chip ana logi digital VLSI systems, researchers worldwide have long realized the vital need of producing advanced computer aided tools for designing both digital and analog circuits and systems for silicon integration. Ar chitecture and circuit compilation, device sizing and the layout genera tion are but a few familiar tasks on the world of digital integrated circuit design which can be efficiently accomplished by matured computer aided tools. In contrast, the art of tools for designing and producing analog or even analogi digital integrated circuits is quite primitive and still lack ing the industrial penetration and acceptance already achieved by digital counterparts. In fact, analog design is commonly perceived to be one of the most knowledge-intensive design tasks and analog circuits are still designed, largely by hand, by expert intimately familiar with nuances of the target application and integrated circuit fabrication process. The techniques needed to build good analog circuits seem to exist solely as expertise invested in individual designers.
Author : Jose G. Delgado-Frias,Will Moore
Publisher : Springer Science & Business Media
Page : 285 pages
File Size : 50,5 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461316190
Author : Stephen W. Director,Wojciech Maly,Andrzej J. Strojwas
Publisher : Springer Science & Business Media
Page : 299 pages
File Size : 54,6 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461315216
One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design". As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.
Author : Carver Mead,Mohammed Ismail
Publisher : Springer Science & Business Media
Page : 250 pages
File Size : 51,7 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461316398
This volume contains the proceedings of a workshop on Analog Integrated Neural Systems held May 8, 1989, in connection with the International Symposium on Circuits and Systems. The presentations were chosen to encompass the entire range of topics currently under study in this exciting new discipline. Stringent acceptance requirements were placed on contributions: (1) each description was required to include detailed characterization of a working chip, and (2) each design was not to have been published previously. In several cases, the status of the project was not known until a few weeks before the meeting date. As a result, some of the most recent innovative work in the field was presented. Because this discipline is evolving rapidly, each project is very much a work in progress. Authors were asked to devote considerable attention to the shortcomings of their designs, as well as to the notable successes they achieved. In this way, other workers can now avoid stumbling into the same traps, and evolution can proceed more rapidly (and less painfully). The chapters in this volume are presented in the same order as the corresponding presentations at the workshop. The first two chapters are concerned with fmding solutions to complex optimization problems under a predefmed set of constraints. The first chapter reports what is, to the best of our knowledge, the first neural-chip design. In each case, the physics of the underlying electronic medium is used to represent a cost function in a natural way, using only nearest-neighbor connectivity.
Author : Vasant B. Rao,David V. Overhauser,Timothy N. Trick,Ibrahim N. Hajj
Publisher : Springer Science & Business Media
Page : 218 pages
File Size : 44,9 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461317098
Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.
Author : Dwight Hill,Don Shugard,John Fishburn,Kurt Keutzer
Publisher : Springer Science & Business Media
Page : 221 pages
File Size : 44,8 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461317074
This book describes a system of VLSI layout tools called IDA which stands for "Integrated Design Aides. " It is not a main-line production CAD environment, but neither is it a paper tool. Rather, IDA is an experimental environment that serves to test out CAD ideas in the crucible of real chip design. Many features have been tried in IDA over the years, some successfully, some not. This book will emphasize the former, and attempt to describe the features that have been useful and effective in building real chips. Before discussing the present state of IDA, it may be helpful to understand how the project got started. Although Bell Labs has traditionally had a large and effective effort in VLSI and CAD, researchers at the Murray Hill facility wanted to study the process of VLSI design independently, emphasizing the idea of small team chip building. So, in 1979 they invited Carver Mead to present his views on MOS chip design, complete with the now famous "lambda" design rules and "tall, thin designers. " To support this course, Steve Johnson (better known for YACC and the portable C compiler) and Sally Browning invented the constraint based "i" language and wrote a compiler for it. A small collection of layout tools developed rapidly around this compiler, including design rule checkers, editors and simulators.