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Author : Li Ding
Publisher : Unknown
Page : 346 pages
File Size : 50,5 Mb
Release : 2004
Category : Electronic
ISBN : UOM:39015056800702
Author : Anonim
Publisher : Unknown
Page : 854 pages
File Size : 49,7 Mb
Release : 2007
Category : Dissertations, Academic
ISBN : STANFORD:36105123442472
Author : Lars Svensson,José Monteiro
Publisher : Springer Science & Business Media
Page : 474 pages
File Size : 54,9 Mb
Release : 2009-02-13
Category : Computers
ISBN : 9783540959472
This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.
Author : Mohamed Elgamel,Magdy A. Bayoumi
Publisher : Springer Science & Business Media
Page : 145 pages
File Size : 40,5 Mb
Release : 2006-03-20
Category : Technology & Engineering
ISBN : 9780387293660
Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
Author : Anonim
Publisher : Institute of Electrical & Electronics Engineers(IEEE)
Page : 846 pages
File Size : 54,6 Mb
Release : 2002
Category : Computers
ISBN : CORNELL:31924093864530
Papers from a January 2002 conference are organized into four sessions each on low power design, synthesis, testing, layout, and interconnects and technology, as well as two sessions each on embedded systems, verification, and VLSI architecture, one session on analog design, and one session on hot c
Author : Bo Fu,Paul Ampadu
Publisher : Springer Science & Business Media
Page : 159 pages
File Size : 52,7 Mb
Release : 2011-10-09
Category : Technology & Engineering
ISBN : 9781441993137
This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.
Author : Anonim
Publisher : Unknown
Page : 876 pages
File Size : 51,6 Mb
Release : 2002
Category : CAD/CAM systems
ISBN : UOM:39015047826618
Author : Rajesh Garg
Publisher : Springer Science & Business Media
Page : 224 pages
File Size : 48,9 Mb
Release : 2009-10-22
Category : Technology & Engineering
ISBN : 9781441909312
This monograph is motivated by the challenges faced in designing reliable VLSI systems in modern VLSI processes. The reliable operation of integrated circuits (ICs) has become increasingly dif?cult to achieve in the deep submicron (DSM) era. With continuouslydecreasing device feature sizes, combinedwith lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations, and radiation-inducedsoft errors. Among these noise sources, soft errors(or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as c- binational logic circuits. Also, in the DSM era, process variations are increasing at a signi?cant rate, making it more dif?cult to design reliable VLSI circuits. Hence, it is important to ef?ciently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this research mo- graph presents several analysis and design techniques with the goal of realizing VLSI circuits, which are radiation and process variation tolerant.
Author : Dan M. Fleetwood
Publisher : World Scientific
Page : 354 pages
File Size : 50,5 Mb
Release : 2004
Category : Technology & Engineering
ISBN : 9812794700
This book provides a detailed treatment of radiation effects in electronic devices, including effects at the material, device, and circuit levels. The emphasis is on transient effects caused by single ionizing particles (single-event effects and soft errors) and effects produced by the cumulative energy deposited by the radiation (total ionizing dose effects). Bipolar (Si and SiGe), metalOCooxideOCosemiconductor (MOS), and compound semiconductor technologies are discussed. In addition to considering the specific issues associated with high-performance devices and technologies, the book includes the background material necessary for understanding radiation effects at a more general level. Contents: Single Event Effects in Avionics and on the Ground (E Normand); Soft Errors in Commercial Integrated Circuits (R C Baumann); System Level Single Event Upset Mitigation Strategies (W F Heidergott); Space Radiation Effects in Optocouplers (R A Reed et al.); The Effects of Space Radiation Exposure on Power MOSFETs: A Review (K Shenai et al.); Total Dose Effects in Linear Bipolar Integrated Circuits (H J Barnaby); Hardness Assurance for Commercial Microelectronics (R L Pease); Switching Oxide Traps (T R Oldham); Online and Realtime Dosimetry Using Optically Stimulated Luminescence (L Dusseau & J Gasiot); and other articles. Readership: Practitioners, researchers, managers and graduate students in electrical and electronic engineering, semiconductor science and technology, and microelectronics."
Author : Amir Zjajo,José Pineda de Gyvez
Publisher : Springer Science & Business Media
Page : 311 pages
File Size : 43,5 Mb
Release : 2010-10-29
Category : Technology & Engineering
ISBN : 9789048197255
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Author : Nadine Azemard,Lars Svensson
Publisher : Springer
Page : 586 pages
File Size : 50,6 Mb
Release : 2007-08-21
Category : Computers
ISBN : 9783540744429
This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Author : Laung-Terng Wang,Cheng-Wen Wu,Xiaoqing Wen
Publisher : Elsevier
Page : 808 pages
File Size : 41,8 Mb
Release : 2006-08-14
Category : Technology & Engineering
ISBN : 0080474799
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Author : Raminderpal Singh
Publisher : John Wiley & Sons
Page : 484 pages
File Size : 53,6 Mb
Release : 2001-12-12
Category : Technology & Engineering
ISBN : 9780471150428
"...offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." —Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc. Covers signal integrity effects in high performance Radio Frequency (RF) IC Brings together research papers from the past few years that address the broad range of issues faced by IC designers and CAD managers now and in the future A Wiley-IEEE Press publication
Author : Robert Aitken
Publisher : Unknown
Page : 524 pages
File Size : 41,6 Mb
Release : 2004
Category : Fault-tolerant computing
ISBN : 0769522416
DFT 2004 showcases the latest research results in the in the field of defect and fault tolerance in VLSI systems. Its papers cover yield, defect and fault tolerance, error correction, and circuit/system reliability and dependability.
Author : Enrico Macii,Vassilis Paliouras,Odysseas Koufopavlou
Publisher : Springer
Page : 916 pages
File Size : 50,8 Mb
Release : 2004-08-24
Category : Technology & Engineering
ISBN : 9783540302056
WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.