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Author : Haihua Su
Publisher : Unknown
Page : 270 pages
File Size : 53,5 Mb
Release : 2002
Category : Electronic
ISBN : MINN:31951P00799654S
Author : Yulei Zhang
Publisher : Unknown
Page : 115 pages
File Size : 40,6 Mb
Release : 2011
Category : Electronic
ISBN : 1124738606
As semiconductor technology advances in the ultra deep sub-micron era, on-chip global interconnections have been an ever-greater barrier to achieving high-performance and low-power for the increasingly larger system-on-chip (SoC) designs. Various on-chip interconnection schemes are proposed to tackle the scaling issue of global wires by manipulating the wire operation regions, changing signaling methods, and applying different equalization techniques. Optimization frameworks are also proposed to aid the transmitter-wire-receiver co-design based on user-defined constraints. For the six representative global interconnection schemes, we investigate their performance metrics with technology scaling by performing optimizations using the proposed SQP-based framework. A set of simple models is also developed to enable early-stage system-level analysis. Performance of different interconnection schemes are predicted and compared over several technology nodes. We further perform studies on the pipelined $RC$ interconnection by exploring its performance metrics with voltage and technology scaling based on different design objectives. A performance evaluation flow is developed to generate the optimal designs for given objectives. Also, impacts of pipelining depth, voltage and technology scaling are illustrated. Finally, we propose an energy-efficient high-speed on-chip global interconnection by employing continuous-time active equalization. Modeling and design of transmitter and receiver circuits are discussed. Analytical formula of received eye-opening is derived for system-level design planning. We further perform transmitter-receiver co-design through an optimization framework and explore the design space to generate design based on best energy-throughput tradeoff.
Author : Ashok K. Goel
Publisher : John Wiley & Sons
Page : 433 pages
File Size : 53,6 Mb
Release : 2007-10-19
Category : Technology & Engineering
ISBN : 9780470165966
This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk. Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include: * Preliminary Concepts * Parasitic Resistances, Capacitances, and Inductances * Interconnection Delays * Crosstalk Analysis * Electromigration-Induced Failure Analysis * Future Interconnections High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.
Author : Konstantin Moiseev,Avinoam Kolodny,Shmuel Wimer
Publisher : Springer
Page : 233 pages
File Size : 53,7 Mb
Release : 2014-11-07
Category : Technology & Engineering
ISBN : 9781461408215
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
Author : Hartmut Grabinski
Publisher : Springer Science & Business Media
Page : 234 pages
File Size : 54,8 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461543497
This book presents an updated selection of the most representative contributions to the 2nd and 3rd IEEE Workshops on Signal Propagation on Interconnects (SPI) which were held in Travemtinde (Baltic See Side), Germany, May 13-15, 1998, and in Titisee-Neustadt (Black Forest), Germany, May 19-21, 1999. This publication addresses the need of developers and researchers in the field of VLSI chip and package design. It offers a survey of current problems regarding the influence of interconnect effects on the electrical performance of electronic circuits and suggests innovative solutions. In this sense the present book represents a continua tion and a supplement to the first book "Signal Propagation on Interconnects", Kluwer Academic Publishers, 1998. The papers in this book cover a wide area of research directions: Beneath the des cription of general trends they deal with the solution of signal integrity problems, the modeling of interconnects, parameter extraction using calculations and measurements and last but not least actual problems in the field of optical interconnects.
Author : Vazgen Melikyan
Publisher : Springer
Page : 365 pages
File Size : 55,5 Mb
Release : 2018-04-12
Category : Technology & Engineering
ISBN : 9783319716374
This book describes new, fuzzy logic-based mathematical apparatus, which enable readers to work with continuous variables, while implementing whole circuit simulations with speed, similar to gate-level simulators and accuracy, similar to circuit-level simulators. The author demonstrates newly developed principles of digital integrated circuit simulation and optimization that take into consideration various external and internal destabilizing factors, influencing the operation of digital ICs. The discussion includes factors including radiation, ambient temperature, electromagnetic fields, and climatic conditions, as well as non-ideality of interconnects and power rails.
Author : Bing Lu,Ding-Zhu Du,S. Sapatnekar
Publisher : Springer Science & Business Media
Page : 292 pages
File Size : 48,9 Mb
Release : 2013-06-29
Category : Computers
ISBN : 9781475734157
Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre sented in Chapter 1. To reduce the run time, different interconnect plan ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.
Author : Ruolong Liu,Electrical Carleton University. Dissertation. Engineering,ProQuest Co
Publisher : Unknown
Page : 198 pages
File Size : 51,5 Mb
Release : 1993
Category : Electronic
ISBN : OCLC:290423354
Author : Dr. Ashad Ullah Qureshi
Publisher : Concepts Books Publication
Page : 33 pages
File Size : 54,7 Mb
Release : 2022-07-01
Category : Technology & Engineering
ISBN : 9798837018565
As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Carbon nanotube (CNT) interconnects have emerged as promising replacement materials for copper interconnects due to their superior conductivity. Buffer insertion for CNT interconnects is capable of improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight CNT, there exist significant unidimensional-spatially correlated variations on the critical CNT geometric parameters such as the diameter and density, which will act the circuit performance. This dissertation develops a novel timing driven buffer insertion technique considering unidimensional correlations of variations of CNT. Although the fabrication variations of CNTs are not desired for the circuit designs targeting performance optimization and reliability, these inherent imperfections make them natural candidates for building highly secure physical unclonable function (PUF), which is an advanced hardware security technology. A novel CNT PUF design through leveraging Lorenz chaotic system is developed and we show that it is resistant to many machine learning modeling attacks. In summary, the studies in this dissertation demonstrate that CNT technology is highly promising for performance and security optimizations in advanced VLSI circuit design.
Author : Sandip Bhattacharya,J Ajayan,Fernando Avila Herrera
Publisher : CRC Press
Page : 223 pages
File Size : 49,8 Mb
Release : 2023-12-22
Category : Technology & Engineering
ISBN : 9781003817062
Focusses on materials and nanomaterials utilization in next generation interconnects based on carbon nanotubes (CNT) and graphene nanoribbons (GNR) Helps readers realize interconnects, interconnect models, and crosstalk noise analysis Describes hybrid CNT and GNR based interconnects Presents the details of power supply voltage drop analysis in CNT and GNR interconnects Overviews pertinent RF performance and stability analysis
Author : Prashant Saxena,Rupesh S. Shelar,Sachin Sapatnekar
Publisher : Springer Science & Business Media
Page : 254 pages
File Size : 53,5 Mb
Release : 2007-04-27
Category : Technology & Engineering
ISBN : 9780387485508
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Author : Jeffrey A. Davis,James D. Meindl
Publisher : Springer Science & Business Media
Page : 417 pages
File Size : 45,8 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461504610
This book is jointly authored by leading academic and industry researchers. The material is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in-depth exploration into interconnect-aware computer architectures.
Author : Rohit Dhiman,Rajeevan Chandel
Publisher : Springer
Page : 113 pages
File Size : 43,6 Mb
Release : 2014-11-07
Category : Technology & Engineering
ISBN : 9788132221326
The book provides a detailed analysis of issues related to sub-threshold interconnect performance from the perspective of analytical approach and design techniques. Particular emphasis is laid on the performance analysis of coupling noise and variability issues in sub-threshold domain to develop efficient compact models. The proposed analytical approach gives physical insight of the parameters affecting the transient behavior of coupled interconnects. Remedial design techniques are also suggested to mitigate the effect of coupling noise. The effects of wire width, spacing between the wires, wire length are thoroughly investigated. In addition, the effect of parameters like driver strength on peak coupling noise has also been analyzed. Process, voltage and temperature variations are prominent factors affecting sub-threshold design and have also been investigated. The process variability analysis has been carried out using parametric analysis, process corner analysis and Monte Carlo technique. The book also provides a qualitative summary of the work reported in the literature by various researchers in the design of digital sub-threshold circuits. This book should be of interest for researchers and graduate students with deeper insights into sub-threshold interconnect models in particular. In this sense, this book will best fit as a text book and/or a reference book for students who are initiated in the area of research and advanced courses in nanotechnology, interconnect design and modeling.
Author : Mohamed Elgamel,Magdy A. Bayoumi
Publisher : Springer Science & Business Media
Page : 145 pages
File Size : 51,9 Mb
Release : 2006-03-20
Category : Technology & Engineering
ISBN : 9780387293660
Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
Author : Stephen Lum,Electrical Carleton University. Dissertation. Engineering,ProQuest Co
Publisher : Unknown
Page : 282 pages
File Size : 54,7 Mb
Release : 1991
Category : Electronic
ISBN : OCLC:290270369