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Author : Donald B. Estreich,Stanford University. Stanford Electronics Laboratories. Integrated Circuits Laboratory
Publisher : Unknown
Page : 344 pages
File Size : 43,5 Mb
Release : 1980
Category : Integrated circuits
ISBN : STANFORD:36105046365768
Author : Nishath K. Verghese,Timothy J. Schmerbeck,David J. Allstot
Publisher : Springer Science & Business Media
Page : 297 pages
File Size : 50,7 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461522393
The goal of putting `systems on a chip' has been a difficult challenge that is only recently being met. Since the world is `analog', putting systems on a chip requires putting analog interfaces on the same chip as digital processing functions. Since some processing functions are accomplished more efficiently in analog circuitry, chips with a large amount of analog and digital circuitry are being designed. Whether a small amount of analog circuitry is combined with varying amounts of digital circuitry or the other way around, the problem encountered in marrying analog and digital circuitry are the same but with different scope. Some of the most prevalent problems are chip/package capacitive and inductive coupling, ringing on the RLC tuned circuits that form the chip/package power supply rails and off-chip drivers and receivers, coupling between circuits through the chip substrate bulk, and radiated emissions from the chip/package interconnects. To aggravate the problems of designers who have to deal with the complexity of mixed-signal coupling there is a lack of verification techniques to simulate the problem. In addition to considering RLC models for the various chip/package/board level parasitics, mixed-signal circuit designers must also model coupling through the common substrate when simulating ICs to obtain an accurate estimate of coupled noise in their designs. Unfortunately, accurate simulation of substrate coupling has only recently begun to receive attention, and techniques for the same are not widely known. Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits addresses two major issues of the mixed-signal coupling problem -- how to simulate it and how to overcome it. It identifies some of the problems that will be encountered, gives examples of actual hardware experiences, offers simulation techniques, and suggests possible solutions. Readers of this book should come away with a clear directive to simulate their design for interactions prior to building the design, versus a `build it and see' mentality.
Author : Norman Einspruch
Publisher : Elsevier
Page : 383 pages
File Size : 42,7 Mb
Release : 2012-12-02
Category : Technology & Engineering
ISBN : 9780323153133
VLSI Electronics Microstructure Science, Volume 18: Advanced MOS Device Physics explores several device physics topics related to metal oxide semiconductor (MOS) technology. The emphasis is on physical description, modeling, and technological implications rather than on the formal aspects of device theory. Special attention is paid to the reliability physics of small-geometry MOSFETs. Comprised of eight chapters, this volume begins with a general picture of MOS technology development from the device and processing points of view. The critical issue of hot-carrier effects is discussed, along with the device engineering aspects of this problem; the emerging low-temperature MOS technology; and the problem of latchup in scaled MOS circuits. Several device models that are suitable for use in circuit simulators are also described. The last chapter examines novel electron transport effects observed in ultra-small MOS structures. This book should prove useful to semiconductor engineers involved in different aspects of MOS technology development, as well as for researchers in this field and students of the corresponding disciplines.
Author : Badih El-Kareh
Publisher : Springer Science & Business Media
Page : 614 pages
File Size : 47,8 Mb
Release : 2009-01-09
Category : Technology & Engineering
ISBN : 9780387690100
Silicon Devices and Process Integration covers state-of-the-art silicon devices, their characteristics, and their interactions with process parameters. It serves as a comprehensive guide which addresses both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. The book is compiled from the author’s industrial and academic lecture notes and reflects years of experience in the development of silicon devices. Features include: A review of silicon properties which provides a foundation for understanding the device properties discussion, including mobility-enhancement by straining silicon; State-of-the-art technologies on high-K gate dielectrics, low-K dielectrics, Cu interconnects, and SiGe BiCMOS; CMOS-only applications, such as subthreshold current and parasitic latch-up; Advanced Enabling processes and process integration. This book is written for engineers and scientists in semiconductor research, development and manufacturing. The problems at the end of each chapter and the numerous charts, figures and tables also make it appropriate for use as a text in graduate and advanced undergraduate courses in electrical engineering and materials science.
Author : Ming-Dou Ker,Sheng-Fu Hsu
Publisher : John Wiley & Sons
Page : 265 pages
File Size : 44,6 Mb
Release : 2009-07-23
Category : Technology & Engineering
ISBN : 9780470824085
The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips. Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process. Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.
Author : Steven H. Voldman
Publisher : John Wiley & Sons
Page : 472 pages
File Size : 47,7 Mb
Release : 2008-04-15
Category : Technology & Engineering
ISBN : 047051616X
Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as: latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids – from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and; examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level. Latchup acts as a companion text to the author’s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.
Author : Badih El-Kareh,Lou N. Hutter
Publisher : Springer
Page : 607 pages
File Size : 49,7 Mb
Release : 2015-06-04
Category : Technology & Engineering
ISBN : 9781493927517
This book covers modern analog components, their characteristics, and interactions with process parameters. It serves as a comprehensive guide, addressing both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. Based on the authors’ extensive experience in the development of analog devices, this book is intended for engineers and scientists in semiconductor research, development and manufacturing. The problems at the end of each chapter and the numerous charts, figures and tables also make it appropriate for use as a text in graduate and advanced undergraduate courses in electrical engineering and materials science.
Author : Steven H. Voldman
Publisher : John Wiley & Sons
Page : 323 pages
File Size : 47,5 Mb
Release : 2016-12-19
Category : Technology & Engineering
ISBN : 9780470511916
With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance. ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup. Key features: Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5. Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP). Describes both conventional testing and new testing techniques for both chip and system level evaluation. Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods. Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing. ESD Testing: From Components to Systems is part of the authors’ series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.
Author : Gerson A. S. Machado
Publisher : IET
Page : 1072 pages
File Size : 52,8 Mb
Release : 1996
Category : Technology & Engineering
ISBN : 0852968744
This book brings together innovative modelling, simulation and design techniques in CMOS, SOI, GaAs and BJT to achieve successful high-yield manufacture for low-power, high-speed and reliable-by-design analogue and mixed-mode integrated systems.
Author : R.R. Troutman
Publisher : Springer Science & Business Media
Page : 255 pages
File Size : 43,9 Mb
Release : 2013-03-14
Category : Technology & Engineering
ISBN : 9781475718874
Why a book on Iatchup? Latchup has been, and continues to be, a potentially serious CMOS reliability concern. This concern is becoming more widespread with the ascendency of CMOS as the dominant VLSI technology, particularly as parasitic bipolar characteristics continue to improve at ever smaller dimensions on silicon wafers with ever lower defect densities. Although many successful parts have been marketed, latchup solutions have often been ad hoc. Although latchup avoidance techniques have been previously itemized, there has been little quantitative evaluation of prior latchup fixes. What is needed is a more general, more systematic treatment of the latchup problem. Because of the wide variety of CMOS technologies and the long term interest in latchup, some overall guiding principles are needed. Appreciating the variety of possible triggering mechanisms is key to a real understanding of latchup. This work reviews the origin of each and its effect on the parasitic structure. Each triggering mechanism is classified according to a new taxonomy.
Author : Steven H. Voldman
Publisher : John Wiley & Sons
Page : 260 pages
File Size : 45,8 Mb
Release : 2011-04-04
Category : Technology & Engineering
ISBN : 9781119992653
Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a ‘top-down' design approach. Look inside for extensive coverage on: integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integration architecturing of mixed voltage, mixed signal, to RF design for ESD analysis floorplanning for peripheral and core I/O designs, and the implications on ESD and latchup guard ring integration for both a ‘bottom-up' and ‘top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to core classification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chip examples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart power practical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics ESD: Design and Synthesis is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
Author : Oleg Semenov,Hossein Sarbishaei,Manoj Sachdev
Publisher : Springer Science & Business Media
Page : 237 pages
File Size : 44,8 Mb
Release : 2008-04-26
Category : Technology & Engineering
ISBN : 9781402083013
ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.
Author : Badih El-Kareh,R.J. Bombard
Publisher : Springer Science & Business Media
Page : 583 pages
File Size : 54,5 Mb
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 9781461322757
There was a long felt need for this book in industrial and academic institutions. It provides new engineers, as well as practicing engineers and advanced laboratory personnel in the field of semiconductors a clear and thorough discussion of state-of-the-art silicon devices, without resorting to the complexity of higher mathematics and physics. This difficult task was made possible by detailing the explanation of equations that describe the device operation and characteristics without endeavoring their full derivation. This is reinforced by several problems which reflect practical cases observed in the laboratory. The problems are given after introducing a major equation or concept. They are arranged in the order of the text rather than in the order of difficulty. The answers to most of the problems are given in order to enable the student to "self-check" the method used for the solutions. The illustrations may prove to be of great help to "newcomers" when dealing with the characterization of real devices and relating the measured data to device physics and process parameters. The new engineer will find the book equivalent to "on the job training" and acquire a working knowledge of the fundamental principles underlying silicon devices. For the engineer with theoretical background, it offers a means for direct application of solid state theory to device analysis and synthesis. The book originated from a set of notes developed for an in-house one-year course in Device Physics, Technology and Characterization at IBM.
Author : Márcio Cherem Schneider,Carlos Galup-Montoro
Publisher : Cambridge University Press
Page : 505 pages
File Size : 46,9 Mb
Release : 2010-01-28
Category : Computers
ISBN : 9780521110365
The essentials of analog circuit design with a unique all-region MOSFET modeling approach.
Author : Elie Maricau,Georges Gielen
Publisher : Springer Science & Business Media
Page : 208 pages
File Size : 51,8 Mb
Release : 2013-01-11
Category : Technology & Engineering
ISBN : 9781461461630
This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.